Servers demand memory that is continually higher performance and lower power while the manufacturing base quickly transitions to sub-20nm process nodes. DRAM refresh-related single bits continue to dominate memory “failure†paretos. However, given appropriate system design these highly unpredictable yet correctable events can be adequately addressed, even with leading edge memory. This discussion will focus on the performance and tradeoffs of implementing ECC and the reliability concerns of refresh-related single bits prevalent in the ramp of new process nodes.
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